What are the FPGA models included in the HC-1.
The HC-1 is organized as follows:
Each of the 4 FPGAs is a Virtex 5 LX330. For more information, see:
Virtex-5 FPGA Family Overview : http://www.xilinx.com/support/documentation/data_sheets/ds100.pdf
Virtex-5 FPGA User Guide: http://www.xilinx.com/support/documentation/user_guides/ug190.pdf
Each of the 8 memory controllers supports two memory channels populated with scatter-gather DIMMs. The coprocessor in our system has a total memory of 16GB.
Here is some basic information from the Virtex 5 LX330 data sheet:
With respect to MitrionC the most important (limiting) resource are the Flip/Flop. Each Virtex-5 FPGA slice contains four LUTs and four flip-flops. Thus the total amount of available F/Fs is 51,840 x 4 = 207,360. Usually an FPGA will have 100% slice utilization at around 50-60% flip-flop usage, thus you can safely count on 103,680 F/Fs (for each FPGA).
Here is an illustration of a Virtex 5 slice.
Each DSP48E slice contains a 25 x 18 multiplier, an adder, and an accumulator.